Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction - researchr publication authors

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Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, Martin Alderton, Jeremy Goldblatt. Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 366-369, IEEE, 2008. [doi]

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