Verification of timed circuits with symbolic delays

Robert Clarisó, Jordi Cortadella. Verification of timed circuits with symbolic delays. In Masaharu Imai, editor, Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004. pages 628-633, IEEE, 2004. [doi]

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