Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Virgile Colrat, David Gaidioz, Andres Asprilla, Frédéric Paillardet, Andreia Cathelin, Yann Deval. Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS. In 17th IEEE Latin America Symposium on Circuits and System, LASCAS 2026, Arequipa, Peru, February 24-27, 2026. pages 1-4, IEEE, 2026. [doi]

This author has not been identified. Look up 'Virgile Colrat' in GoogleThis author has not been identified. Look up 'David Gaidioz' in GoogleThis author has not been identified. Look up 'Andres Asprilla' in GoogleThis author has not been identified. Look up 'Frédéric Paillardet' in GoogleThis author has not been identified. Look up 'Andreia Cathelin' in GoogleThis author has not been identified. Look up 'Yann Deval' in Google

runs on WebDSL