Virgile Colrat, David Gaidioz, Andres Asprilla, Frédéric Paillardet, Andreia Cathelin, Yann Deval. Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS. In 17th IEEE Latin America Symposium on Circuits and System, LASCAS 2026, Arequipa, Peru, February 24-27, 2026. pages 1-4, IEEE, 2026. [doi]
Abstract is missing.