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A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation

James Coole, John Wernsing, Greg Stitt. A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. In Viktor K. Prasanna, Lionel Torres, René Cumplido, editors, ReConFig 09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings. pages 143-148, IEEE Computer Society, 2009. [doi]

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James Coole

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John Wernsing

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Greg Stitt

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