Table of Contents

• A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGALei Wang, Lei Chen, Zhiping Wen, Huabo Sun, Shuo Wang. 1-5 [doi]
• FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point MultiplierMalte Baesler, Thomas Teufel. 6-11 [doi]
• Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable ArchitecturesSven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, Wolfgang Rosenstiel. 12-17 [doi]
• MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAsYoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli. 18-23 [doi]
• Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and AreaTaciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes. 24-29 [doi]
• A 10 Gbps OTN Framer Implementation Targeting FPGA DevicesGuilherme Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes. 30-35 [doi]
• FPGA Implementations of BCD MultipliersGustavo Sutter, Elias Todorovich, Gery Bioul, M. Vazquez, Jean-Pierre Deschamps. 36-41 [doi]
• Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT ImplementationsM. Vazquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps. 42-47 [doi]
• Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator ArchitectureJiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing. 48-53 [doi]
• PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable SystemsArmando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez. 54-58 [doi]
• A FPGA IEEE-754-2008 Decimal64 Floating-Point MultiplierCarlos Minchola, Gustavo Sutter. 59-64 [doi]
• Speeding up Fault Injection for Asynchronous Logic by FPGA-Based EmulationMarcus Jeitler, Jakob Lechner. 65-70 [doi]
• Runtime Memory Allocation in a Heterogeneous Reconfigurable PlatformVlad Mihai Sima, Koen Bertels. 71-76 [doi]
• A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation TasksRafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman. 77-82 [doi]
• A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAsAlireza Rohani, Hamid R. Zarandi. 83-88 [doi]
• Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved PerformanceAdwait Gupte, Phillip Jones. 89-94 [doi]
• Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian NetworkMingjie Lin, Yaling Ma. 95-100 [doi]
• FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet AnalysisE. Cabal-Yepez, Roque A. Osornio-Rios, René de Jesús Romero-Troncoso, J. R. Razo-Hernandez, R. Lopez-Garcia. 101-106 [doi]
• A Scalable Architecture for Multivariate Polynomial Evaluation on FPGAMathieu Allard, Patrick Grogan, Jean-Pierre David. 107-112 [doi]
• An FPGA-Based Custom High Performance Interconnection NetworkMondrian Nüssle, Benjamin Geib, Holger Fröning, Ulrich Brüning. 113-118 [doi]
• Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000Tobias Schumacher, Tim Suss, Christian Plessl, Marco Platzner. 119-124 [doi]
• A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGAHideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri. 125-130 [doi]
• Scalability Studies of the BLASTn Scan and Ungapped Extension FunctionsSiddhartha Datta, Ron Sass. 131-136 [doi]
• Low Power RTL Exploration Mechanism Based on the Cache ParametersAbel G. Silva-Filho, Sidney M. L. Lima, F. C. L. Cox. 137-142 [doi]
• A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body SimulationJames Coole, John Wernsing, Greg Stitt. 143-148 [doi]
• Low Power, Reconfigurable Computing Platform for SpacecraftGuillermo Conde, Gregory W. Donohoe, Siva Maheswaran. 149-154 [doi]
• Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data StructureNaoki Tanida, Mary Inaba, Kei Hiraki, Takeshi Yoshino. 155-160 [doi]
• Triple Line-Based Playout for Go - An Accelerator for Monte Carlo GoKenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe. 161-166 [doi]
• Acceleration of Fractal Image Compression Using the Hardware-Software Co-design MethodologyOscar Alvarado Nava, Arturo Díaz-Pérez. 167-171 [doi]
• FPGA Implementation of the Generalized Hough TransformSergio Ruben Geninatti, Jose Ignacio Benavides Benitez, Manuel Hernandez Calvino, Nicolás Guil Mata, Juan Gómez-Luna. 172-177 [doi]
• An Optimized System for Multiple Sequence AlignmentCaglar Yilmaz, Mustafa Gök. 178-182 [doi]
• Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic ImplementationsJulien Bringer, Hervé Chabanne, Jean-Luc Danger. 183-188 [doi]
• Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable ModulesStephanie Drzevitzky, Uwe Kastens, Marco Platzner. 189-194 [doi]
• Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and PeripheralsMarcio Juliato, Catherine H. Gebotys. 195-200 [doi]
• Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and RoutingEmna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez. 201-206 [doi]
• Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic AlgorithmsAhmet Onur Durahim, Erkay Savas, Kazim Yumbul. 207-212 [doi]
• Combined SCA and DFA Countermeasures Integrable in a FPGA Design FlowShivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane. 213-218 [doi]
• Efficient Technique for the FPGA Implementation of the AES MixColumns TransformationSolmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz. 219-224 [doi]
• Lightweight Cryptography for FPGAsPanasayya Yalla, Jens-Peter Kaps. 225-230 [doi]
• Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional UnitsAntoine Trouve, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki Murakami. 231-236 [doi]
• Observing the Randomness in RO-Based TRNGNathalie Bochard, Florent Bernard, Viktor Fischer. 237-242 [doi]
• DPL on Stratix II FPGA: What to Expect?Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu. 243-248 [doi]
• FPGA Implementation of an Elliptic Curve Processor Using the GLV MethodMark Hamilton, William P. Marnane. 249-254 [doi]
• Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECCBrian Baldwin, William P. Marnane, Robert Granger. 255-260 [doi]
• Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier DatapathJohann Großschädl, Erkay Savas, Kazim Yumbul. 261-266 [doi]
• A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous FloorplansVitor de Paulo, Cristinel Ababei. 267-272 [doi]
• Overview of FPGA-Based Multiprocessor SystemsTaho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa. 273-278 [doi]
• Symmetric Multiprocessor Systems on FPGAPablo Huerta, Javier Castillo, Cesar Pedraza, Javier Cano, José Ignacio Martínez. 279-283 [doi]
• A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-ChipHung-Manh Pham, Sébastien Pillement, Didier Demigny. 284-289 [doi]
• Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-ChipsArghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy. 290-295 [doi]
• Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration ManagerR. Dafali, Jean-Philippe Diguet. 296-301 [doi]
• High-Level FPGA Programming through Mapping Process Networks to FPGA ResourcesFritz Mayer-Lindenberg. 302-307 [doi]
• Efficient PGA LFSR Implementation Whitens Pseudorandom NumbersLeonard Colavito, Dennis Silage. 308-313 [doi]
• Composite Look-Up Table Gaussian Pseudo-Random Number GeneratorLeonard Colavito, Dennis Silage. 314-319 [doi]
• Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP StandardHector Borrayo-Sandoval, Ramon Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe. 320-325 [doi]
• High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps ProcessorMark E. Dunham, Zachary Baker, Matthew Stettler, Michael Pigue, Paul S. Graham, Eric N. Schmierer, John Power. 326-331 [doi]
• A Dynamically Reconfigurable Platform for Fixed-Point FIR FiltersDaniel Llamocca, Marios S. Pattichis, G. Alonzo Vera. 332-337 [doi]
• Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP ApplicationsChenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall. 338-343 [doi]
• A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable ElementsAsadollah Shahbahrami, Mahmood Ahmadi, Stephan Wong, Koen Bertels. 344-349 [doi]
• Enhancing the Productivity of Radio Designers with RapidRadioJorge Surís, Adolfo Recio, Peter Athanas. 350-355 [doi]
• Signal Processing Domain Application Mapping on the Brick Reconfigurable ArrayJuan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi. 356-361 [doi]
• Multiprocessor Task Migration Implementation in a Reconfigurable PlatformLaurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet. 362-367 [doi]
• Virtualization of Computing Resources in RCS for Multi-task Stream ApplicationsLev Kirischian, Victor Dumitriu, Pil Woo Chun. 368-373 [doi]
• Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration TimeAbelardo Jara-Berrocal, Ann Gordon-Ross. 374-379 [doi]
• Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on ChipMuhammad Aqeel Wahlah, Kees G. W. Goossens. 380-385 [doi]
• New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGAJulien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy. 386-391 [doi]
• Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGAJochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick. 392-397 [doi]
• Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot ControllerMark G. Arnold, Jung H. Cho. 398-403 [doi]
• A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot MappingJohn A. Kalomiros, John N. Lygouras. 404-409 [doi]
• Fuzzy Control for Cyclist Robot Stability Using FPGAsC. Yesid E. Castro, Carlos H. Llanos, Walter de Britto Vidal Filho, Leandro dos Santos Coelho. 410-415 [doi]
• FPGA Implementation for Direct Kinematics of a Spherical Robot ManipulatorDiego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Jose M. Motta. 416-421 [doi]
• On the Implementation of Central Pattern Generators for Periodic Rhythmic LocomotionCesar Torres-Huitzil. 422-426 [doi]
• Bio-inspired Self-Testing and Self-Organizing Bit Slice ProcessorsAndré Stauffer, Joël Rossier. 427-432 [doi]
• Effects of Simplistic Online Synthesis for AMIDAR ProcessorsStefan Döbrich, Christian Hochberger. 433-438 [doi]
• A Reconfigurable Design Framework for FPGA Adaptive ComputingMing Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch. 439-444 [doi]
• Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware ArchitectureJ. Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany. 445-450 [doi]
• FPGA Implementation of Izhikevich Spiking Neural Networks for Character RecognitionKenneth L. Rice, Mohammad A. Bhuiyan, Tarek M. Taha, Christopher N. Vutsinas, Melissa C. Smith. 451-456 [doi]