A. Cortiula, D. Scubla, S. Murra, D. Menin, A. Bandiziol, F. Driussi, P. Palestri. Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS. In 20th International Conference on PhD Research in Microelectronics and Electronics, PRIME 2025, Taormina, Italy, September 21-24, 2025. pages 1-4, IEEE, 2025. [doi]
Abstract is missing.