Jan Craninckx, Geert Van der Plas. A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 246-600, IEEE, 2007. [doi]
@inproceedings{CraninckxP07,
title = {A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS},
author = {Jan Craninckx and Geert Van der Plas},
year = {2007},
doi = {10.1109/ISSCC.2007.373386},
url = {http://dx.doi.org/10.1109/ISSCC.2007.373386},
researchr = {https://researchr.org/publication/CraninckxP07},
cites = {0},
citedby = {0},
pages = {246-600},
booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
publisher = {IEEE},
isbn = {1-4244-0853-9},
}