Area-efficient parallel decoder architecture for high rate QC-LDPC codes

Zhiqiang Cui, Zhongfeng Wang. Area-efficient parallel decoder architecture for high rate QC-LDPC codes. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Abstract

Abstract is missing.