A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch - researchr publication related

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K. Wayne Current. A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. In ISMVL. pages 168-173, 1990.

The following publications are possibly variants of this publication:

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full AddersK. Wayne Current. TC, 29(5):400-403, 1980.

Four-valued threshold logic full adder circuit implementationsK. Wayne Current, Douglas A. Mow. ismvl 1978: 95-100 [doi]

Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder CircuitsJames L. Mangin, K. Wayne Current. TC, 35(2):157-161, 1986.

Design of a Quaternary Latch Circuit Using a Binary CMOS RS LatchK. Wayne Current. ismvl 2000: 377-381 [doi]

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