A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator - researchr publication related

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Sai Manoj P. D., Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu. A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator. IEEE Trans. on Circuits and Systems, 64-I(6):1432-1443, 2017. [doi]

The following publications are possibly variants of this publication:

A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and MemorySai Manoj P. D., Hao Yu, Hantao Huang, Dongjun Xu. TC, 65(4):1185-1196, 2016. [doi]

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