Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh. Soft Error-Aware Power Optimization Using Gate Sizing. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 255-267, Springer, 2007. [doi]
Abstract is missing.