Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam. Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. In Gordon J. Brebner, Roger Woods, editors, Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings. Volume 2147 of Lecture Notes in Computer Science, pages 315-325, Springer, 2001. [doi]
Abstract is missing.