Performance Comparison of VLSI Adders Using Logical Effort

Hoang Q. Dao, Vojin G. Oklobdzija. Performance Comparison of VLSI Adders Using Logical Effort. In Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido, editors, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Volume 2451 of Lecture Notes in Computer Science, pages 25-34, Springer, 2002. [doi]

Abstract

Abstract is missing.