A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. J. Solid-State Circuits, 57(12):3538-3551, 2022. [doi]

@article{DartizioBTASISC22-0,
  title = {A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time},
  author = {Simone Mattia Dartizio and Francesco Buccoleri and Francesco Tesolin and Luca Avallone and Alessio Santiccioli and Agata Iesurum and Giovanni Steffan and Dmytro Cherniak and Luca Bertulessi and Andrea Bevilacqua and Carlo Samori and Andrea L. Lacaita and Salvatore Levantino},
  year = {2022},
  doi = {10.1109/JSSC.2022.3206955},
  url = {https://doi.org/10.1109/JSSC.2022.3206955},
  researchr = {https://researchr.org/publication/DartizioBTASISC22-0},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {57},
  number = {12},
  pages = {3538-3551},
}