A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. In IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. pages 78-79, IEEE, 2023. [doi]

@inproceedings{DartizioTCBLRCBSLL23,
  title = {A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering},
  author = {Simone Mattia Dartizio and Francesco Tesolin and Giacomo Castoro and Francesco Buccoleri and Luca Lanzoni and Michele Resson and Dmytro Cherniak and Luca Bertulessi and Carlo Samori and Andrea L. Lacaita and Salvatore Levantino},
  year = {2023},
  doi = {10.1109/ISSCC42615.2023.10067719},
  url = {https://doi.org/10.1109/ISSCC42615.2023.10067719},
  researchr = {https://researchr.org/publication/DartizioTCBLRCBSLL23},
  cites = {0},
  citedby = {0},
  pages = {78-79},
  booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023},
  publisher = {IEEE},
  isbn = {978-1-6654-9016-0},
}