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Shirshendu Das, Hemangee K. Kapoor. Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. In 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017. pages 182-187, IEEE, 2017. [doi]