Tanay Das, Madhav Pathak, Sandip Lashkare. Dynamic Resistance Reduction Methods for Voltage Clamp Lowering to Enhance GGNMOS ESD Protection. In 28th International Symposium on VLSI Design and Test, VDAT 2024, Vellore, India, September 1-3, 2024. pages 1-5, IEEE, 2024. [doi]
Abstract is missing.