Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk. Modeling post-techmapping and post-clustering FPGA circuit depth. In Martin Danek, Jiri Kadlec, Brent E. Nelson, editors, 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic. pages 205-211, IEEE, 2009. [doi]
@inproceedings{DasWLL09, title = {Modeling post-techmapping and post-clustering FPGA circuit depth}, author = {Joydip Das and Steven J. E. Wilton and Philip Heng Wai Leong and Wayne Luk}, year = {2009}, doi = {10.1109/FPL.2009.5272315}, url = {http://dx.doi.org/10.1109/FPL.2009.5272315}, tags = {modeling}, researchr = {https://researchr.org/publication/DasWLL09}, cites = {0}, citedby = {0}, pages = {205-211}, booktitle = {19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic}, editor = {Martin Danek and Jiri Kadlec and Brent E. Nelson}, publisher = {IEEE}, isbn = {978-1-4244-3892-1}, }