High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Aravind Dasu, Arvind Sudarsanam. High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications. In 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CA, USA. IEEE Computer Society, 2005. [doi]

This author has not been identified. Look up 'Aravind Dasu' in GoogleThis author has not been identified. Look up 'Arvind Sudarsanam' in Google

runs on WebDSL