Aravind Dasu, Arvind Sudarsanam. High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications. In 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CA, USA. IEEE Computer Society, 2005. [doi]
@inproceedings{DasuS05,
title = {High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications},
author = {Aravind Dasu and Arvind Sudarsanam},
year = {2005},
doi = {10.1109/IPDPS.2005.242},
url = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.242},
tags = {architecture, analysis, design},
researchr = {https://researchr.org/publication/DasuS05},
cites = {0},
citedby = {0},
booktitle = {19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2312-9},
}