Abstract is missing.
- SSIM: A Software Levelized Compiled-Code SimulatorL.-T. Wang, Nathan E. Hoover, Edwin H. Porter, John J. Zasio. 2-8 [doi]
- Requirements for a Practical Software Engineering EnvironmentV. Masurkar. 67-73 [doi]
- A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout GeneratorN. J. Elias. 82-88 [doi]
- Transistor Sizing in CMOS CircuitsMehmet A. Cirit. 121-124 [doi]
- A Three-Layer Gridless Channel Router with CompactionD. B. Polkl. 146-151 [doi]
- A Practical Moat RouterR. K. McGehee. 216-222 [doi]
- An Automated Design of Minimum-Area IC Power/Ground NetsS. Chowdhury. 223-229 [doi]
- Switch Directed Dynamic Causal Networks - a Paradigm for Electronic System DiagnosisR. M. McDermott, D. Stern. 258-264 [doi]
- Tutorial: Reading and Reviewing the Common Schema for Electrical Design and AnalysisC. H. Parks. 479-483 [doi]
- The IBM VHDL Design SystemL. F. Saunders. 484-490 [doi]
- ASTA: LSI Design Management SystemT. Ogihara, H. Toyoshima, S. Murai. 530-536 [doi]
- Automated Layout Generation Using Gate Matrix ApproachY. C. Chang, S.-C. Chang, L.-H. Hsu. 552-558 [doi]
- Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation MechanismsM. L. Brei. 565-565 [doi]
- The Implementation of a State Machine CompilerC. Kingsley. 580-583 [doi]
- PALMINI - Fast Boolean Minimizer for Personal ComputersL. B. Nguyen, M. A. Perkowdki, N. B. Goldstein. 615-621 [doi]
- A gridless Variable-Width Channel Router for Marco Cell DesignC.-H. Ng. 633-636 [doi]
- PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor PlacementW.-J. Lue, Lawrence P. McNamee. 659-665 [doi]
- PAMS: An Expert System for Parameterized Module SynthesisT. Cesear, E. Iodice, C. Tsareff. 666-671 [doi]
- An Expert System Application in Semicustom VLSI DesignR. L. Steele. 679-688 [doi]
- A Parts Selection Expert System to Increase ManufacturabilityD. Praizler, G. Fritz. 706-712 [doi]
- A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit BoardsE. Rosenberg. 721-726 [doi]
- Heuristic Acceleration of Force-Directed PlacementR. Forbes. 735-740 [doi]
- Optimal Layout to Avoid CMOS Stuck-Open FaultsS. Koeppe. 829-835 [doi]