Dieison Antonello Deprá, Sergio Bampi. Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis. In Jürgen Becker, Marcelo O. Johann, Ricardo Reis, editors, VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers. Volume 360 of IFIP Publications, pages 181-197, Springer, 2009. [doi]
Abstract is missing.