Combining Instruction and Loop Level Parallelism for FPGAs

Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. Combining Instruction and Loop Level Parallelism for FPGAs. In The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001. pages 273-282, IEEE, 2001. [doi]

Abstract

Abstract is missing.