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Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs

Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne Burleson. Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 242-247, IEEE, 2016. [doi]

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Kapil Dev

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Sherief Reda

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Indrani Paul

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Wei Huang

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Wayne Burleson

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