Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne Burleson. Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016. pages 242-247, IEEE, 2016. [doi]
@inproceedings{DevRPHB16,
title = {Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs},
author = {Kapil Dev and Sherief Reda and Indrani Paul and Wei Huang and Wayne Burleson},
year = {2016},
doi = {10.1109/ISVLSI.2016.60},
url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2016.60},
researchr = {https://researchr.org/publication/DevRPHB16},
cites = {0},
citedby = {0},
pages = {242-247},
booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9039-2},
}