Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test - researchr publication authors

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V. R. Devanathan, C. P. Ravikumar, V. Kamakoti. Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA. pages 167-172, IEEE Computer Society, 2007. [doi]

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