Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 3-8, ACM, 2011. [doi]

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