Krishnendu Dhar. Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology. In 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014. pages 600-606, IEEE, 2014. [doi]
@inproceedings{Dhar14,
title = {Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology},
author = {Krishnendu Dhar},
year = {2014},
doi = {10.1109/ICACCI.2014.6968212},
url = {http://dx.doi.org/10.1109/ICACCI.2014.6968212},
researchr = {https://researchr.org/publication/Dhar14},
cites = {0},
citedby = {0},
pages = {600-606},
booktitle = {2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014},
publisher = {IEEE},
isbn = {978-1-4799-3078-4},
}