A Memory-Efficient NTT Accelerator with a Highly Parallel Memory Mapping Scheme - researchr publication authors

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Hengyu Ding, Houran Ji, Jia Li, Jinhang Chen, Chiu-Wing Sham, Yao Wang 0013. A Memory-Efficient NTT Accelerator with a Highly Parallel Memory Mapping Scheme. In IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, May 24-28, 2026. pages 3351-3355, IEEE, 2026. [doi]

This author has not been identified. Look up 'Hengyu Ding' in GoogleThis author has not been identified. Look up 'Houran Ji' in GoogleThis author has not been identified. Look up 'Jia Li' in GoogleThis author has not been identified. Look up 'Jinhang Chen' in GoogleThis author has not been identified. Look up 'Chiu-Wing Sham' in GoogleThis author has not been identified. Look up 'Yao Wang 0013' in Google

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