An area efficient low power ECoG front-end chip for digitalized subdural grid

Chenjie Dong, Han Jin, Ikhwan Kim, Chenyu Wang, Yajie Qin, Lirong Zheng. An area efficient low power ECoG front-end chip for digitalized subdural grid. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 444-447, IEEE, 2017. [doi]

Authors

Chenjie Dong

This author has not been identified. Look up 'Chenjie Dong' in Google

Han Jin

This author has not been identified. Look up 'Han Jin' in Google

Ikhwan Kim

This author has not been identified. Look up 'Ikhwan Kim' in Google

Chenyu Wang

This author has not been identified. Look up 'Chenyu Wang' in Google

Yajie Qin

This author has not been identified. Look up 'Yajie Qin' in Google

Lirong Zheng

This author has not been identified. Look up 'Lirong Zheng' in Google