A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier

Achille Donida, Piero Malcovati, Remy Cellier, Angelo Nagari, Andrea Baschirotto. A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier. In 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, December 8-11, 2013. pages 437-440, IEEE, 2013. [doi]

Abstract

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