The following publications are possibly variants of this publication:
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- Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADCS. M. Mayur, R. K. Siddharth, Kumar Y. B. Nithin, M. H. Vasantha. isvlsi 2017: 600-603 [doi]
- Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input SwingSumit Khalapure, R. K. Siddharth, Kumar Y. B. Nithin, M. H. Vasantha. isvlsi 2017: 585-588 [doi]
- Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance ApplicationsSiddharth R. K., Y. B. Nithin Kumar, M. H. Vasantha. sncs, 1(6):310, 2020. [doi]