Design and Implementation of High Speed Arithmetic Coder Architecture of JPEG2000 on Reconfigurable FPGA - researchr publication

researchr

You are not signed in
Sign in
Sign up

M. F. Ebian, E. Elsehley, A. E. Elhenawy. Design and Implementation of High Speed Arithmetic Coder Architecture of JPEG2000 on Reconfigurable FPGA. In Reneta P. Barneva, Valentin E. Brimkov, editors, Image Analysis - From Theory to Applications. Proceedings of IWCIA 2008 Special Track on Applications, Buffalo, NY, USA, April 7-9, 2008. pages 235-241, Research Publishing, 2008.

Abstract is missing.

runs on WebDSL