A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits

Seyed Milad Ebrahimipour, Behnam Ghavami, Mohsen Raji. A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits. IEEE Trans. Emerging Topics Comput., 9(2):759-773, 2021. [doi]

Abstract

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