Applying Logic Synthesis for Speeding Up SAT

Niklas Eén, Alan Mishchenko, Niklas Sörensson. Applying Logic Synthesis for Speeding Up SAT. In João Marques-Silva, Karem A. Sakallah, editors, Theory and Applications of Satisfiability Testing - SAT 2007, 10th International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings. Volume 4501 of Lecture Notes in Computer Science, pages 272-286, Springer, 2007. [doi]

@inproceedings{EenMS07,
  title = {Applying Logic Synthesis for Speeding Up SAT},
  author = {Niklas Eén and Alan Mishchenko and Niklas Sörensson},
  year = {2007},
  doi = {10.1007/978-3-540-72788-0_26},
  url = {http://dx.doi.org/10.1007/978-3-540-72788-0_26},
  tags = {logic},
  researchr = {https://researchr.org/publication/EenMS07},
  cites = {0},
  citedby = {0},
  pages = {272-286},
  booktitle = {Theory and Applications of Satisfiability Testing - SAT 2007, 10th International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings},
  editor = {João Marques-Silva and Karem A. Sakallah},
  volume = {4501},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {978-3-540-72787-3},
}