Florian Eibensteiner, Jürgen Kogler, Josef Scharinger. A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform. In IEEE Conference on Computer Vision and Pattern Recognition, CVPR Workshops 2014, Columbus, OH, USA, June 23-28, 2014. pages 637-644, IEEE, 2014. [doi]
@inproceedings{EibensteinerKS14,
title = {A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform},
author = {Florian Eibensteiner and Jürgen Kogler and Josef Scharinger},
year = {2014},
doi = {10.1109/CVPRW.2014.97},
url = {http://dx.doi.org/10.1109/CVPRW.2014.97},
researchr = {https://researchr.org/publication/EibensteinerKS14},
cites = {0},
citedby = {0},
pages = {637-644},
booktitle = {IEEE Conference on Computer Vision and Pattern Recognition, CVPR Workshops 2014, Columbus, OH, USA, June 23-28, 2014},
publisher = {IEEE},
}