Allocating registers in multiple instruction-issuing processors

Christine Eisenbeis, Franco Gasperoni, Uwe Schwiegelshohn. Allocating registers in multiple instruction-issuing processors. In Lubomir Bic, Paraskevas Evripidou, A. P. Wim Böhm, Jean-Luc Gaudiot, editors, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, PACT '95, Limassol, Cyprus, June 27-29, 1995. pages 290-293, IFIP Working Group on Algol / ACM, 1995. [doi]

@inproceedings{EisenbeisGS95,
  title = {Allocating registers in multiple instruction-issuing processors},
  author = {Christine Eisenbeis and Franco Gasperoni and Uwe Schwiegelshohn},
  year = {1995},
  url = {http://dl.acm.org/citation.cfm?id=224948},
  researchr = {https://researchr.org/publication/EisenbeisGS95},
  cites = {0},
  citedby = {0},
  pages = {290-293},
  booktitle = {Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, PACT '95, Limassol, Cyprus, June 27-29, 1995},
  editor = {Lubomir Bic and Paraskevas Evripidou and A. P. Wim Böhm and Jean-Luc Gaudiot},
  publisher = {IFIP Working Group on Algol / ACM},
}