Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio. A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. J. Solid-State Circuits, 46(9):2084-2098, 2011. [doi]
@article{ElsayedDGSS11,
title = {A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator},
author = {Mohamed M. Elsayed and Vijay Dhanasekaran and Manisha Gambhir and José Silva-Martínez and Edgar Sánchez-Sinencio},
year = {2011},
doi = {10.1109/JSSC.2011.2156990},
url = {http://dx.doi.org/10.1109/JSSC.2011.2156990},
researchr = {https://researchr.org/publication/ElsayedDGSS11},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {46},
number = {9},
pages = {2084-2098},
}