A multi-bit error tolerant register file for a high reliable embedded processor

Siamak Esmaeeli, Morteza Hosseini, Bijan Vosoughi Vahdat, Bizhan Rashidian. A multi-bit error tolerant register file for a high reliable embedded processor. In 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011. pages 532-537, IEEE, 2011. [doi]

Authors

Siamak Esmaeeli

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Morteza Hosseini

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Bijan Vosoughi Vahdat

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Bizhan Rashidian

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