Hans Eveking, Tobias Dornes, Martin Schweikert. Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. In Zeljko Zilic, Sandeep K. Shukla, editors, 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011. pages 17-24, IEEE, 2011. [doi]
Abstract is missing.