A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter

S. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders. A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter. In Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, October 26-28, 2015. pages 1-4, IEEE, 2015. [doi]

@inproceedings{FahmyDSOA15,
  title = {A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter},
  author = {S. Fahmy and Markus Dietl and Puneet Sareen and Maurits Ortmanns and Jens Anders},
  year = {2015},
  doi = {10.1109/NORCHIP.2015.7364357},
  url = {https://doi.org/10.1109/NORCHIP.2015.7364357},
  researchr = {https://researchr.org/publication/FahmyDSOA15},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP & International Symposium on System-on-Chip (SoC), Oslo, Norway, October 26-28, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-6576-5},
}