A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS

Chao Fan, Wei-Han Yu, Pui-In Mak, Rui P. Martins. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. IEEE Trans. on Circuits and Systems, 66-I(12):4850-4861, 2019. [doi]

@article{FanYMM19,
  title = {A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS},
  author = {Chao Fan and Wei-Han Yu and Pui-In Mak and Rui P. Martins},
  year = {2019},
  doi = {10.1109/TCSI.2019.2936226},
  url = {https://doi.org/10.1109/TCSI.2019.2936226},
  researchr = {https://researchr.org/publication/FanYMM19},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {66-I},
  number = {12},
  pages = {4850-4861},
}