A Parallel Simulated Annealing Approach for Floorplanning in VLSI - researchr publication authors

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Jyh Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han. A Parallel Simulated Annealing Approach for Floorplanning in VLSI. In Arrems Hua, Shih-Liang Chang, editors, Algorithms and Architectures for Parallel Processing, 9th International Conference, ICA3PP 2009, Taipei, Taiwan, June 8-11, 2009. Proceedings. Volume 5574 of Lecture Notes in Computer Science, pages 291-302, Springer, 2009. [doi]

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