Jyh Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han. A Parallel Simulated Annealing Approach for Floorplanning in VLSI. In Arrems Hua, Shih-Liang Chang, editors, Algorithms and Architectures for Parallel Processing, 9th International Conference, ICA3PP 2009, Taipei, Taiwan, June 8-11, 2009. Proceedings. Volume 5574 of Lecture Notes in Computer Science, pages 291-302, Springer, 2009. [doi]
@inproceedings{FangCCLHSH09,
title = {A Parallel Simulated Annealing Approach for Floorplanning in VLSI},
author = {Jyh Perng Fang and Yang-Lang Chang and Chih-Chia Chen and Wen-Yew Liang and Tung-Ju Hsieh and Muhammad T. Satria and Chin-Chuan Han},
year = {2009},
doi = {10.1007/978-3-642-03095-6_29},
url = {http://dx.doi.org/10.1007/978-3-642-03095-6_29},
tags = {systematic-approach},
researchr = {https://researchr.org/publication/FangCCLHSH09},
cites = {0},
citedby = {0},
pages = {291-302},
booktitle = {Algorithms and Architectures for Parallel Processing, 9th International Conference, ICA3PP 2009, Taipei, Taiwan, June 8-11, 2009. Proceedings},
editor = {Arrems Hua and Shih-Liang Chang},
volume = {5574},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-03094-9},
}