Testability profile estimation of VLSI circuits from fault coverage

H. A. Farhat, H. Saidian. Testability profile estimation of VLSI circuits from fault coverage. In First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991. pages 238-242, IEEE, 1991. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.