Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits - researchr publication authors

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Michael Figueiredo, Tomasz Michalak, João Goes, Luís Gomes, Pawel Sniatala. Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits. In 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunesia, 13-19 December, 2009. pages 763-766, IEEE, 2009. [doi]

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