Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

Michael Figueiredo, Tomasz Michalak, João Goes, Luís Gomes, Pawel Sniatala. Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits. In 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunesia, 13-19 December, 2009. pages 763-766, IEEE, 2009. [doi]

@inproceedings{FigueiredoMGGS09,
  title = {Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits},
  author = {Michael Figueiredo and Tomasz Michalak and João Goes and Luís Gomes and Pawel Sniatala},
  year = {2009},
  doi = {10.1109/ICECS.2009.5410771},
  url = {http://dx.doi.org/10.1109/ICECS.2009.5410771},
  researchr = {https://researchr.org/publication/FigueiredoMGGS09},
  cites = {0},
  citedby = {0},
  pages = {763-766},
  booktitle = {16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunesia, 13-19 December, 2009},
  publisher = {IEEE},
  isbn = {978-1-4244-5090-9},
}