A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators - researchr publication

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Ryan F. Forelli, Rui Shi, Seda Ogrenci, Joshua Agar. A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators. In 42nd IEEE VLSI Test Symposium, VTS 2024, Tempe, AZ, USA, April 22-24, 2024. pages 1-5, IEEE, 2024. [doi]

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