A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET

Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang. A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. In 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. pages 1-2, IEEE, 2016. [doi]

@inproceedings{FransEHIKPSUZAB16,
  title = {A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET},
  author = {Yohan Frans and Mohamed Elzeftawi and Hiva Hedayati and Jay Im and Vassili Kireev and Toan Pham and Jaewook Shin and Parag Upadhyaya and Lei Zhou and Santiago Asuncion and Chris Borrelli and Geoff Zhang and Hongtao Zhang and Ken Chang},
  year = {2016},
  doi = {10.1109/VLSIC.2016.7573474},
  url = {http://dx.doi.org/10.1109/VLSIC.2016.7573474},
  researchr = {https://researchr.org/publication/FransEHIKPSUZAB16},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-0635-9},
}